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Figure 5.4. Read operation form Low Energy Peripherals
Core Clock Dom ain
Low Frequency Clock Dom ain
Core Clock
Register 0
Register 1
.
.
.
Register n
Freeze
Low Frequency Clock
Synchronizer 0
Synchronizer 1
.
.
.
Synchronizer n
Low Frequency Clock
Register 0 Sync
Register 1 Sync
.
.
.
Register n Sync
HW Status Register 0
Read
Synchronizer
HW Status Register 1
.
.
.
Low Energy
Peripheral
Main
Function
HW Status Register m
Read Data
5.3.2 FREEZE register
In all Low Energy Peripheral there is a <module_name>_FREEZE register (e.g. RTC_FREEZE). The
register contains a bit named REGFREEZE. If precise control of the synchronization process is required,
this bit may be utilized. When REGFREEZE is set, the synchronization process is halted allowing
the software to write multiple Low Energy registers before starting the synchronization process, thus
providing precise control of the module update process. The synchronization process is started by
clearing the REGFREEZE bit.
5.4 Flash
The Flash retains data in any state and typically stores the application code, special user data and
security information. The Flash memory is typically programmed through the debug interface, but can
also be erased and written to from software.
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?
?
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Up to 128 KB of memory
Page size of 512 bytes (minimum erase unit)
Minimum 20K erase cycles endurance
Greater than 10 years data retention at 85°C
Lock-bits for memory protection
Data retention in any state
5.5 SRAM
The primary task of the SRAM memory is to store application data. Additionally, it is possible to execute
instructions from SRAM, and the DMA may be set up to transfer data between the SRAM, Flash and
peripherals.
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Up to 16 KB memory
Bit-band access support
4KB blocks may be individually powered down when not in use
Data retention of the entire memory in EM0 to EM3
2011-04-12 - d0001_Rev1.10
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